1. Field of the Invention
The invention relates generally to the semiconductor devices. More particularly, this invention relates to a novel and improved manufacture method and device configuration for achieve low cost package of a semiconductor device such as a power device comprising metal-oxide semiconductor field effect transistors (MOSFET) chips.
2. Description of the Prior Art
Conventional techniques for containing and protecting a chip formed as an integrated circuit (IC) device in a package are confronted with several limitations. First limitation is the areas that such package occupies is several times larger than the IC chip. The size of the package thus imposes a limitation on the miniaturization of the electronic devices that implement such package. Furthermore, the cost of conventional chip packaging is relatively high due to the fact that each chip must be individually processed applying the single device handling techniques.
Specific example of conventional package of a semiconductor device is the wire-bonding package of a power MOSFET device. The packaging processes are consuming and costly. The extra wire connections further increase the resistance and reduce the performance and meanwhile generate more heat during device operations. In order to overcome such difficulties and limitations, many prior art patents disclose different configuration and packaging processes to reduce the size and cost of manufacturing. Many of such prior art disclosures further provide methods and device configurations to improve the performance characteristics by reducing the resistance and inductance of connections.
In U.S. Pat. No. 6,166,434, entitled “Die Chip Assembly for Semiconductor Package”, Desai, et al. disclose a die clip for use in semiconductor flip chip packaging as a replacement for the conventional combination of a heat spreader and stiffener, a packaging method using the die clip, and a semiconductor package incorporating the die clip. In a preferred embodiment, the die clip is a piece of high modulus, high thermal conductivity material shaped to attach over a die on the surface of a packaging substrate. The die clip closely engages the die while leaving some space open around the perimeter to provide access to the die. The packaging configuration as disclosed however cannot be conveniently applied to the power MOSFET chips due to the fact that there are no gate and source paths. The packaging configuration as disclosed would have resistances even higher than the gold or aluminum wires currently implemented for the MOSFET chips. The higher resistances are caused by the small size of the bumps or the balls due to the limitations of the size of the die. Higher resistances are resulted from attachment of small bumps or balls to the board when the bump or balls have very limited contact areas to the board. Furthermore, the packaging configuration as disclosed would make the board level assembly joints difficult to assemble because both the bumps or balls on the flip chips and the cap will have different claps height during the assembly process. Potential problems with board level reliability may arise due to these height differences.
In U.S. Pat. No. 6,624,522, entitled “Chip scale surface mounted device and process of manufacture”, Standing, et al. disclose a chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom. The packaging configuration as disclosed however has limited heat dissipation areas. Furthermore, the exposed portions of the electrode surface for soldering contact will result in resistances and inductances that would degrade the performance of the power MOSFET device.
Therefore, a need still exists for those of ordinary skill in the art to provide a new and improved packaging configuration and processing methods such that the above discussed limitations and difficulties can be resolved. Specifically, it is desirable that an improved packaging configuration and processing method is able to achieve low cost, reduce size and improved performance for a power MOSFET device.